1. Field of the Invention
The present invention relates to an output buffer of an electronic device, and more particularly, to an output buffer for reducing production cost of the electronic device.
2. Description of the Prior Art
Output buffers are widely used in electronic devices to separate a signal input terminal and a signal output terminal, for decreasing influences from the load and enhancing driving capability. Please refer to FIG. 1, which is a schematic diagram of an output buffer 10 according to the prior art. The output buffer 10 comprises an input terminal 100, an OR gate 102, an AND gate 104, delay cells 106, 108, a p-type metal-oxide-semiconductor (PMOS) transistor 110, an n-type metal-oxide-semiconductor (NMOS) transistor 112 and an output terminal 114. The OR gate 102 is utilized for performing an OR operation on an input signal SI from the input terminal 100 and a gate control signal VN from the delay cell 108, for outputting an operation result to the delay cell 106. The delay cell 106 delays the output of the operation result, for generating a gate control signal VP. Similarly, the AND gate 104 is utilized for performing an AND operation on the input signal SI and the gate control signal VP from the delay cell 106, for outputting an operation result to the delay cell 108. The delay cell 108 delays the output of the operation result, for generating the gate control signal VN. The gate control signal VP and VN controls the conduction of the PMOS transistor 110 and the NMOS transistor 112 for generating an output signal SO. The output terminal 114 outputs the output signal SO to the load.
Please refer to FIG. 2, which is a timing diagram of the input signal SI, the output signal SO, the gate control signal VP and VN. As shown in FIG. 2, by using the OR gate 102 and the delay cell 106, the PMOS transistor 110 first conducts according to the gate control signal VP at a time point T2, then by using the AND gate and the delay cell 108, the NMOS transistor 112 conducts according to the gate control signal VN at a time point T3. In other words, the PMOS transistor 110 and the NMOS transistor 112 conduct and turn off at different times so as to implement the non-overlapping output function. A lot of components are required to implement the OR gate 102, the AND gate 104, the delay cells 106 and 108, however. As a result, production cost of the output buffer 10 cannot be reduced.